This disclosure relates to technology for forming semiconductor features.
Forming features in semiconductor circuits such as dense patterns of lines can present problems. Semiconductor device geometries continue to scale smaller and smaller, which presents even further difficulties. As the gaps between features become smaller and the aspect ratios of gap depth to width becomes greater it becomes harder to fill the gaps. For example, when filling a high aspect ratio gap the dielectric material may clog the top of the gap before it is filled. Therefore, a void may form.
Materials and techniques have been developed to prevent or reduce voids from forming due to the dielectric material clogging. For example, flowable dielectrics have been developed that work very well to fill narrow gap, high aspect ratio patterns. Some of these fill materials need a treatment, such as curing after deposition. The curing may outgas residual components, reduce the dielectric constant, complete formation of chemical bonds, etc. For example, a flowable CVD (Chemical Vapor Deposition) oxide may be treated with a high temperature steam anneal to convert the flowable CVD oxide to silicon oxide. Another technique for filling narrow gap, high aspect ratio patterns is a spin-on-dielectric (SOD). A SOD may be subjected to an ultraviolet radiation curing process.